As one example of the structure of a memory cell in a nonvolatile semiconductor memory device, a metal/oxide film/nitride film/oxide film/semiconductor (MONOS) structure in which interference between adjacent memory cells is suppressed is provided (for example, see Jp-A 2009-16615 (KOKAI).
The MONOS memory cell is a defined as a memory cell in which a charge storage layer is formed of an insulating body having a charge trap function. Therefore, a structure in which the charge storage layer is formed above the upper surface of a semiconductor layer with a tunnel insulating film disposed therebetween and a control gate electrode is formed above the upper surface of the charge storage layer with a charge block layer disposed therebetween is provided.
At the erase operation time of the MONOS memory cell, the semiconductor layer is grounded and a negative voltage is applied to the control gate electrode. By setting the above voltage relation, holes are injected from the semiconductor layer into the charge storage layer. Therefore, electrons stored in the charge storage layer will disappear.
In the memory cell, insulation of the charge block layer is not complete. Therefore, electrons will leak from the control gate electrode towards the semiconductor layer at the erase operation time. Electrons having leaked from the control gate electrode are accelerated until they reach the interface of the tunnel insulating film/semiconductor layer and gain a great amount of energy. Thus, the electrons are impact-ionized in the semiconductor layer. Therefore, damage is done to the tunnel insulating film and the interface of the tunnel insulating film/semiconductor layer and insulation of the tunnel insulating film is degraded. As a result, there occurs a problem that the charge holding characteristic of the memory cell will be degraded.